LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY bike_light_1 IS
	PORT
	(clk_in:IN STD_LOGIC;
	--start:IN STD_LOGIC;
	--reset:IN STD_LOGIC;
	out_cat:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
	out_seg:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
	out_row,out_r,out_g:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
	turn_left,turn_right,recover,stop,poweroff:in std_logic;
	buzzer:out std_logic;
	LCD_RS :    out std_logic; --寄存器选择信号
	LCD_RW :    out std_logic; --液晶读写信号
	LCD_EN :    out std_logic; --液晶时钟信号
	lcd_data:  out std_logic_vector(7 downto 0); --液晶数据信号
	--record_switch,next_record:IN STD_LOGIC
	record_switch,record_1,record_2,record_3:IN STD_LOGIC
	);
END;

ARCHITECTURE struct OF bike_light_1 IS
	COMPONENT fenpin
	PORT(
	clk:IN STD_LOGIC;
	--clear:IN STD_LOGIC;
	clk_out1:OUT STD_LOGIC;
	clk_out2:OUT STD_LOGIC;
	clk_out3:OUT STD_LOGIC;
	clk_out4:OUT STD_LOGIC;
	clk_1MHz,clk_4Hz:OUT STD_LOGIC;
	pulse_out:OUT STD_LOGIC
	);
	END COMPONENT;
	
	COMPONENT jishi
	PORT
(	--start:	IN STD_LOGIC;
	clk_in:IN STD_LOGIC;
	sec_outl:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	sec_outh:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	sec_decimalh,sec_decimall:OUT INTEGER RANGE 0 TO 9;
	state_in:IN INTEGER RANGE 0 TO 4;
	state_out:OUT STD_LOGIC
	--counttest:OUT INTEGER RANGE 99 DOWNTO 0--for debug
);
	END COMPONENT;
	
	COMPONENT led_select
	PORT(
	sech,secl:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	clk_select:IN STD_LOGIC;
	q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);--select which led segment will be lighten 
	dataout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)--select what number led will show
	);
	END COMPONENT;
	
	COMPONENT led_show
	PORT
	(count:	IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	seg7:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
	);
	END COMPONENT;
	
	COMPONENT shake_prv2
	port(
		clk : in std_logic;
		btn_in : in std_logic;
		btn_out : out std_logic
	);
	END COMPONENT;
	
	COMPONENT show_control
	port(
	clk:in std_logic;
	clk_4hz:in std_logic;
	pulse:in std_logic;
	cnt_qiehuan:in integer range 0 to 2;
	row:out std_logic_vector(7 downto 0);
	red:out std_logic_vector(7 downto 0);
	green:out std_logic_vector(7 downto 0);
	state:in integer range 0 to 4
	);
	END COMPONENT;
	
	COMPONENT huxideng
	port(CLK:in STD_LOGIC;
         --Q :out STD_LOGIC_VECTOR(7 DOWNTO 0);
         Q:OUT STD_LOGIC;
         row:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
         cnt_qiehuan:OUT INTEGER RANGE 0 TO 2
         ); 
    END COMPONENT;
    
    COMPONENT state_control
	port(
	clk:in std_logic;
	clk_second:in std_logic;
	turn_left,turn_right,recover,stop,poweroff:in std_logic;
	--count_down:in integer range 0 to 9;
	state:out integer range 0 to 4;--0:opening music,1:running,2:turn_left,3:turn_right,4:stop
	--state_save:out integer range 0 to 4
	save_flag:out std_logic
	);
	END COMPONENT;
	
	COMPONENT music_player
	port(clk : in std_logic;--1mhz
		--TN : in std_logic_vector(3 downto 0);--音符编码
		spks : out std_logic;
		clk_4hz:in std_logic;--0.25s per musical note
		--A : BUFFER STD_LOGIC_VECTOR(8 DOWNTO 0);
		state:IN INTEGER RANGE 0 TO 4
		);
	END COMPONENT;
	
	COMPONENT lcd_show2 
	PORT(clk:IN STD_LOGIC;
	state_in:IN INTEGER RANGE 0 TO 4;
	sech_decode,secl_decode:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	rs,rw,en:OUT STD_LOGIC;
	data:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
	--q:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	--rdaddress:BUFFER STD_LOGIC_VECTOR(4 DOWNTO 0);
	ram_in0,ram_in1,ram_in2,ram_in3,ram_in4,ram_in5,ram_in6,ram_in7,ram_in8:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	record_switch:IN STD_LOGIC;
	--next_record:IN STD_LOGIC
	record_1,record_2,record_3:IN STD_LOGIC
	);
	end component;
	
	COMPONENT lcd_decode
	port 
	(
	sech,secl:in integer range 0 to 9;
	sech_decode,secl_decode:out std_logic_vector(7 downto 0)
	);
	END COMPONENT;
	
	--COMPONENT driving_record
	--PORT
	--(
		--clock		: IN STD_LOGIC ;
		--data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		--rdaddress		: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
		--wraddress		: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
		--wren		: IN STD_LOGIC  := '1';
		--q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	--);
	--END COMPONENT;
	
	COMPONENT data_merge2
	port(
	--clk:in std_logic;--100hz
	state_save:in integer range 0 to 4;
	sech_save,secl_save:in std_logic_vector(7 downto 0);
	save_flag:in std_logic;
	--data_ram:out std_logic_vector(7 downto 0);
	--wren:out std_logic;
	--wraddress:out std_logic_vector(4 downto 0)
	ram_out0,ram_out1,ram_out2,ram_out3,ram_out4,ram_out5,ram_out6,ram_out7,ram_out8:out std_logic_vector(7 downto 0)
	);
	END COMPONENT;
	
	SIGNAL clk_temp1:STD_LOGIC;
	SIGNAL clk_temp2:STD_LOGIC;
	SIGNAL clk_temp3:STD_LOGIC;
	SIGNAL clk_temp4:STD_LOGIC;
	SIGNAL pulse_temp:STD_LOGIC;
	SIGNAL data_templ:STD_LOGIC_VECTOR(3 DOWNTO 0);
	SIGNAL data_temph:STD_LOGIC_VECTOR(3 DOWNTO 0);
	SIGNAL data_out:STD_LOGIC_VECTOR(3 DOWNTO 0);
	SIGNAL jishistate:STD_LOGIC;
	--SIGNAL start_prv:STD_LOGIC;
	SIGNAL qtemp:STD_LOGIC;
	SIGNAL cnt_qiehuan:INTEGER RANGE 0 TO 2;
	SIGNAL state_temp:INTEGER RANGE 0 TO 4;
	SIGNAL clk_4Hz,clk_1MHz:STD_LOGIC;
	SIGNAL sec_decimalh,sec_decimall:INTEGER RANGE 0 TO 9;
	SIGNAL sech_decode,secl_decode:STD_LOGIC_VECTOR(7 DOWNTO 0);
	--SIGNAL wren:STD_LOGIC;
	--SIGNAL data_ram_temp:STD_LOGIC_VECTOR(7 DOWNTO 0);
	--SIGNAL rdaddress_temp,wraddress_temp:STD_LOGIC_VECTOR(4 DOWNTO 0);
	--SIGNAL q_temp2:STD_LOGIC_VECTOR(7 DOWNTO 0);
	SIGNAL ram_temp0,ram_temp1,ram_temp2,ram_temp3,ram_temp4,ram_temp5,ram_temp6,ram_temp7,ram_temp8:STD_LOGIC_VECTOR(7 DOWNTO 0);
	SIGNAL save_flag:std_logic;
	--SIGNAL stop_prv,next_record_prv,turn_left_prv,turn_right_prv,recover_prv,start_prv:std_logic;
	SIGNAL stop_prv,turn_left_prv,turn_right_prv,recover_prv,start_prv,record_1_prv,record_2_prv,record_3_prv:std_logic;

	BEGIN
	u0:fenpin port map(clk=>clk_in,clk_out1=>clk_temp1,clk_out2=>clk_temp2,clk_out3=>clk_temp3,clk_out4=>clk_temp4,pulse_out=>pulse_temp,clk_4Hz=>clk_4Hz,clk_1MHz=>clk_1Mhz);
	u1:shake_prv2 port map(clk_temp1,stop,stop_prv);
	--u2:shake_prv2 port map(clk_temp1,next_record,next_record_prv);
	u12:shake_prv2 port map(clk_temp1,turn_left,turn_left_prv);
	u13:shake_prv2 port map(clk_temp1,turn_right,turn_right_prv);
	u14:shake_prv2 port map(clk_temp1,recover,recover_prv);
	--u15:shake_prv2 port map(clk_temp1,start,start_prv);
	u17:shake_prv2 port map(clk_temp1,record_1,record_1_prv);
	u18:shake_prv2 port map(clk_temp1,record_2,record_2_prv);
	u19:shake_prv2 port map(clk_temp1,record_3,record_3_prv);
	u3:jishi port map(clk_in=>clk_temp2,state_out=>jishistate,sec_outl=>data_templ,sec_outh=>data_temph,state_in=>state_temp,sec_decimalh=>sec_decimalh,sec_decimall=>sec_decimall);
	u4:led_select port map(clk_select=>clk_temp1,secl=>data_templ,sech=>data_temph,q=>out_cat,dataout=>data_out);
	u5:led_show port map(count=>data_out,seg7=>out_seg);
	u6:show_control port map(clk=>clk_in,pulse=>qtemp,row=>out_row,red=>out_r,green=>out_g,cnt_qiehuan=>cnt_qiehuan,state=>state_temp,clk_4hz=>clk_4Hz);
	u7:huxideng port map(CLK=>clk_temp3,Q=>qtemp,cnt_qiehuan=>cnt_qiehuan);
	u8:state_control port map(clk_second=>clk_temp2,clk=>clk_in,turn_left=>turn_left_prv,turn_right=>turn_right_prv,recover=>recover_prv,stop=>stop_prv,poweroff=>poweroff,state=>state_temp,save_flag=>save_flag);
	u9:music_player port map(clk=>clk_1Mhz,clk_4hz=>clk_4Hz,spks=>buzzer,state=>state_temp);
	u10:lcd_decode port map(sech=>sec_decimalh,secl=>sec_decimall,sech_decode=>sech_decode,secl_decode=>secl_decode);
	u11:lcd_show2 port map(clk=>clk_in,rs=>LCD_RS,rw=>LCD_RW,en=>LCD_EN,data=>lcd_data,sech_decode=>sech_decode,secl_decode=>secl_decode,state_in=>state_temp,record_switch=>record_switch,record_1=>record_1_prv,record_2=>record_2_prv,record_3=>record_3_prv,ram_in0=>ram_temp0,ram_in1=>ram_temp1,ram_in2=>ram_temp2,ram_in3=>ram_temp3,ram_in4=>ram_temp4,ram_in5=>ram_temp5,ram_in6=>ram_temp6,ram_in7=>ram_temp7,ram_in8=>ram_temp8);
	--u12:driving_record port map(clock=>clk_in,wren=>wren,data=>data_ram_temp,rdaddress=>rdaddress_temp,wraddress=>wraddress_temp,q=>q_temp2);
	u16:data_merge2 port map(state_save=>state_temp,sech_save=>sech_decode,secl_save=>secl_decode,ram_out0=>ram_temp0,ram_out1=>ram_temp1,ram_out2=>ram_temp2,ram_out3=>ram_temp3,ram_out4=>ram_temp4,ram_out5=>ram_temp5,ram_out6=>ram_temp6,ram_out7=>ram_temp7,ram_out8=>ram_temp8,save_flag=>save_flag);
	END;
	
	